1. Field of Invention
The present invention relates to a voltage-reducing device, and more particularly, to a device connecting to a voltage source, which device provides a reduced voltage suitable for use in the manufacturing processes of semiconductor elements.
2. Description of Related Art
With the steady improvement in semiconductor technologies, the dimensions of IC devices are greatly reduced thanks to higher integration density. The primary objective in the manufacturing of semiconductor elements now becomes the efficient utilization of a limited space so that more elements can be incorporated into an IC device.
Refer to FIG. 1, which shows a circuit diagram of a static random access memory (SRAM) cell designed using a well-known NMOS technology. This SRAM cell is implemented using 4 transistors, M1, M2, M3 and M4. Transistors M1 and M2 are driving transistors, while transistors M3 and M4 are used for data access in the memory. As shown in FIG. 1, transistors M1 and M2 are coupled to a biased voltage source V.sub.cc, while transistors M3 and M4 have their gates coupled to a word line. The voltage of the word line, which is for data access, is also 5 volts. Since the operation of the SRAM is not our concern in this invention, it is not described herein. Note that, however, the voltage used by every transistor in this circuit is 5 volts. Thus, the design rule for every transistor is the same.
FIG. 2 shows a circuit diagram of a SRAM cell designed using a well-known CMOS technology. The structure of this circuit is the same as FIG. 1, except that two PMOS transistors, M5 and M6, serve as the load. Hence, the same design rule applies to every transistor since the operation principles are the same as FIG. 1.
Generally speaking, transistors M3 and M4 need to be connected to a word line. They are therefore required to tolerate the voltage from the voltage source (5 volts for example). However, transistors M1 and M2 used as driving transistors need not be constrained by this condition, and are allowed to adopt a lower biased voltage (3 volts for example) to perform well. Unfortunately, this characteristic is always neglected, and the same design rule for every transistor is employed instead, which therefore increases the dimension of the SRAM cell and reduces the space utilization efficiency within a die.
In another aspect, it is well-known that a different circuit structure or layout can be used to implement a particular design object. It is quite normal that several versions of a die with the same functions are screened by comparing their characteristics so as to find a better design method before mass production. The most suitable die among the versions is then chosen for mass production. However, there is no an objective comparison base if these dies are produced on different wafers, since the ingredients and manufacturing environment for every wafer can be quite different. To minimize the errors due to environmental factors, different versions of a die are fabricated on the same wafer in practical application. Though this kind of arrangement is more objective for version comparison, it also causes difficulties for distinction when the dies are cut and mixed together.
In light of the foregoing, there is a need to provide a device to distinguish dies from different versions.